Responsibilities to Include:

BIST integration and verification
Test logic design and verification
Atpg test coverage investigation.
Atpg pattern generation.
Back annotated test vector simulation debug.
Test program bring-up and debug

Qualifications, Skills and Experience

Experience in DFT/Atpg
RTL and gatelevel debug/verification.
Experience in using Mentor Modelsim simulator
Experience in using Synopsys Tetramax tool
Scripting skills, preferably Perl
An Electronic Engineering Degree or equivalent

If this is of interest, please call Jon on 01753 828 914 and send your CV to jonmdarg for more information.

Please note, you will only be considered if you are an EU national or if you hold a valid Tier-1 work permit or equivalent.