Job Title: Senior ASIC Design Engineer
Position: Permanent, Full time
Location: Dresden, Germany
Salary Range: DOE
Responsibilities:
-Collaboration in the definition and further development of our RF system-on-chip architecture
-Responsibility for the RTL design of digital blocks and their integration at system level
-Close cooperation with the analog/RF team to implement highly integrated RF ASICs
-Development and implementation of functional verification at block and chip level
-Support with qualification, testing and ramp-up of our chips
-Documentation of the development processes and results
Requirements:
-Completed studies in electrical engineering, microelectronics or a comparable field of study
-Sound knowledge of ASIC digital design, in particular SoC integration
-Good knowledge of SystemVerilog, Verilog or VHDL
-Experience in the development and application of modern verification methods (e.g. UVM)
-Ideally experience in working with mixed-signal design teams
-Knowledge of synthesis and timing analysis is an advantage
-Collaboration in an international team - therefore good English skills are required
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