Job Title: Senior RTL Design Engineer
Position: Permanent
Location: France, Aix En Provence
Salary Range: DOE
Client Information:
A premier chip and silicon IP provider.
Seeking a motivated full-time Senior RTL Design Engineer to join our PCIe, CXL, AMBA controller IP design team.
You’ll be reporting to the PCIe, CXL, AMBA controller IP Design Manager.
You’ll contribute to the architecture, design of next generation IPs, targeting the latest developments in PCIe, CXL and AMBA standards.
Responsibilities:
-Contribute to the architecture and micro-architecture of next generation PCIe / CXL / AMBA controller IP
-Implement these designs in System Verilog
-Collaborate with the verification team to verify the IPs
-Participate in prototyping of the IPs in cutting edge FPGAs
Requirements:
-MINIMUM of 7+ years of experience with RTL Design
-RTL coding: Verilog / System Verilog
-Master's degree (Minimal education) in Electrical Engineering, Computer Engineering or equivalent.
-7+ years of experience with RTL Design
-Good English skills, communication skills, and willingness to work with an international team.
-Knowledge of AMBA AXI or similar bus protocols
Additional Desirable requirements:
-FPGA flows : Vivado / Quartus
-Continuous Integration : Python / Jenkins / GIT
-Knowledge of PCIe / CXL
-Linux OS knowledge
THIS ROLE WILL NOT BE PROVIDING VISA SPONSORSHIP. EU CITIZENS ONLY.
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